- Developed open-source software libraries and example designs in C++ to demonstrate how to use the SmartHLS compiler (see Github)
- Provided technical support to internal customers and FAEs on how to use SmartHLS
- Became familiar with FPGA debugging through JTAG, and created and filed a patent for an automatic FPGA instrumentation tool
- Wrote a custom Python tool to parse code comments and resource usage reports into documentation
- Maintained CI infrastructure that automated end-to-end (from C++ to RTL compilation to running on the FPGAs) tests using Jenkins and Docker
- Led the Toronto office social committee and planned social events for the Toronto office

- Became familiar with FPGA packing, placement, routing, and timing analysis
- Created, tested, and debugged VPR command line options
- Used C++ and Glade to create a graphical interface to visualise chip floorplanning constraints
- Refactored codebase and updated it from C standards to C++ standards